There is known a duty ratio correcting circuit having an input buffer for clock to which a first clock signal is input, and an input buffer for data to which a first data signal is input (refer to Patent Document 1). A duty adjusting circuit for clock adjusts, based on a correction signal, a duty ratio of a second clock signal output from the input buffer for clock, to thereby generate a third clock signal. A duty adjusting circuit for data adjusts, based on the correction signal, a duty ratio of a second data signal output from the input buffer for data, to thereby generate a third data signal. A duty comparison circuit generates the correction signal based on the third clock signal.
Further, there is known a clock/data recovery circuit having a data duty correcting circuit for outputting correction data obtained by correcting the duty of input data according to the level of a correction signal (refer to Patent Document 2). A clock recovery circuit generates a recovered clock synchronized with the edge timing of the correction data. A data identifying circuit identifies the correction data by the recovered clock. A data duty detecting circuit detects the duty of the correction data by the recovered clock and outputs the correction signal indicating a duty correction amount to the data duty correcting circuit.
Patent Document 1: Japanese Laid-open Patent Publication No. 2010-206348
Patent Document 2: International Publication Pamphlet No. WO 2008/111241
A duty cycle distortion (DCD) is a distortion caused when a pulse width of data of 1 and a pulse width of data of 0 are different. When data is generated based on a clock signal, even if a duty ratio of the clock signal is corrected to 50%, a duty cycle distortion sometimes occurs in the data.